This invention relates to adaptive finite impulse response (FIR) filters, and more particularly, to adaptive FIR filters using time multiplexed multipliers with multiple coefficients per multiplier and which implement burst mode updating of the filter coefficients.
Prior art finite impulse response (FIR) filters employ fixed delay lines for recirculating the coefficients. Such delay lines are implemented using a series of edge triggered flip flops. As a result, in operation, the prior art delay lines consume more power than is desirable.
In copending U.S. patent application Ser. No. 08/937665, assigned to the same assignee as the instant application, multiported register files are employed to implement the coefficient storage and to provide the delays in the coefficients that are necessary for filter operation. A multiported register file is a memory, typically small, e.g., having a capacity for four words, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register file may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port. In regards to coefficients, each multiported register file feeds data from one output to the multiply-add portion of its associated stage of the FIR filter. Note that these outputs may be the same. For coefficient use, there is no need to operate the register file in the lookthrough mode described in the copending application.
When the FIR filter is an adaptive filter with updatable coefficients, it is necessary to have an update unit which computes new coefficient values.
In addition, multiported register files of the prior copending application circulated all of the bits of the coefficients all of the time. Each bit of the coefficient that is circulated requires incremental power consumption.
We have recognized that improved multiported register files may be used for storing coefficients in adaptive FIR filters. In accordance with the principles of the invention, the multiported register files of prior copending application are improved upon by implementing a split memory architecture, with the ability to separately control the least significant bits and the most significant bits of coefficient values that are stored in the filter. When the filter is operated to use so-called xe2x80x9cburst modexe2x80x9d updatingxe2x80x94such as disclosed in U.S. Pat. No. 5,646,957 issued to Im et al., assigned to the same assignee as the present invention, which is incorporated by reference as if fully set forth hereinxe2x80x94which only requires updating when predefined error conditions are encountered, the updating circuitry of the filter can be disabled and only the most significant bits of the coefficients are read out from the multiported register file while the least significant bits remain unchanged. This conserves power without sacrificing precision, since only certain ones of the bits of the coefficients are used in the multiplication of the sample. In addition, in accordance with an aspect of the invention, when only the most significant bits of the coefficients are being cycled through the multiported register filter, any changing bits are prevented from being supplied to the updating circuit, so that the updating circuit performs no computation at all, rather than performing one that is discarded. Advantageously, using such improved multiported register files, adaptive FIR filters can be constructed which operate with lower power consumption.
Additionally, the split architecture and disabling techniques may be used to provide advantages in architectures that use recirculating registers, such as the aforementioned